(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing the via resistance of copper damascene interconnect plugs.
(2) Description of the Prior Art
In creating very and ultra large scale integration (VLSI and ULSI) semiconductor circuits, one of the more important aspects of this creation is the fabrication of metal interconnect lines and vias that provide the interconnection of integrated circuits in semiconductor devices. The invention specifically addresses the creation of conductive vias using the damascene process.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. The conventional dual damascene process requires two masking steps to form first the via pattern after which the pattern for the conductive lines is formed.
Using the dual damascene process, an insulating layer or a dielectric layer, such as silicon oxide, is patterned with a multiplicity of openings for conductive lines and vias. The openings are simultaneously filled with a metal, such as aluminum, and serve to interconnect the active and/or the passive elements of an integrated circuit. The dual damascene process is also used for forming multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted. Critical to a good dual damascene structure is that the edges of the via openings in the lower half of the insulating layer are clearly defined. Furthermore, the alignment of the two masks is critical to assure that the pattern for the conductive lines aligns with the pattern of the vias. This requires a relatively large tolerance while the via may not extend over the full width of the conductive line.
FIG. 1a gives an overview of the steps of the damascene process, as follows:
step 01 shows the formation of the metal plug,
step 02 shows the deposition of the Intra-Level Dielectric (ILD),
step 03 shows the formation of the trenches for metal lines,
step 04 shows the deposition of metal to fill the trenches, and
step 05 shows the removal of metal from the surface.
The damascene process is further explained below, the numbers indicated within this explanation refer to the cross section of a damascene structure that is shown in FIG. 1b. 
Referring now specifically to FIG. 1a, step 01, there is shown the formation of a metal via plug 10 in the surface of a semiconductor substrate 14 (FIG. 1b). Any micro-scratch in the surface of the substrate 14 will fill with metal during subsequent metal deposition and can cause electrical shorts between adjacent via plugs 10 or between electrical lines deposited on top of surface 12. To remove the damascene residue and to remove the scratch count on the surface 12, surface 12 is polished and buffed after the metal plug 10 has been created.
FIG. 1a, step 02 shows the deposition of the Intra-Level Dielectric (ILD) 16 (FIG. 1b) which can be deposited using Plasma Enhanced CVD (PECVD) technology. Dielectric 16 can, for instance, be SiO2.
FIG. 1a, step 03 shows the formation of the trenches 22 (FIG. 1b) for the metal lines, these trenches 22 can be formed using Reactive Ion Etching (RIE) technology.
FIG. 1a, step 04 shows the deposition of metal to fill the trenches 22, this process can use either the CVD or a metal flow process. The excess metal on the surface 26 is removed using the CMP process, see FIG. 1a, step 05, and a planar structure 26 with metal inlays 22 in the intra-level dielectric 16 is achieved.
For many of the applications of the damascene process, a thin barrier layer is deposited over the inside of the opening for the damascene conducting line (thereby covering the bottom and the sidewalls of this opening) prior to the formation of the damascene conducting line. Frequently used material for this barrier layer is TaN/Ta. This layer of TaN/Ta prevents diffusion of the copper of conducting line into the surrounding dielectric during the formation of the copper conducting line. The barrier layer typically has a thickness of about 300 Angstrom.
In addition, a copper seed layer can be deposited over the surface of the barrier layer, this seed copper facilitates and enhances the formation of the copper conducting line during its deposition. A copper seed layer typically has a thickness of about 1600 Angstrom.
The damascene process, as already indicated above, first etches the conductor pattern into the dielectric after which the etched pattern is filled with metal to create the buried metalization that also has a surface of good planarity. This damascene process also eliminates the need of a dielectric deposition in order to fill the gaps. A planarized metal deposition process can be used for this to fill the pattern that has been created in a dielectric layer of SiO2. An etchback or CMP process will remove the excess metal over the field regions. CMP thereby offers the advantage of providing a globally planarized surface. The indicated processing steps can be applied to both single and dual damascene.
For the dual damascene process, the processing steps can follow three approaches. The dual damascene structure consists of a lower (via plug) part and an upper (interconnect line) part.
Approach 1, the via is created first. This approach uses a double layer stack of dielectric whereby the layers of dielectric are separated by an etch stop layer typically containing SiN. A lowest etch stop layer is deposited over the surface of the substrate on which the dual damascene structure is to be created, this lowest etch stop layer is the etch stop for the via etch. The vias are formed by resist patterning after which an etch through the double layer dielectric stack is performed. This is followed by patterning the conductor (interconnect line) in the top layer of SiO2 thereby using the inter-dielectric etch stop layer of SiN as the etch stop layer.
Approach 2, the conductor first process. The conductor patterns is formed by resist patterning and by etching the conductor patterns into the upper SiO2 layer thereby using the SiN layer as an etch stop layer. This is followed by via resist patterning and etching through the thin layer of SiN and the lower SiO2 layer.
Approach 3, the etch stop layer first. The first SiO2 layer is deposited, followed by the thin layer of SiN as etch stop, followed by the via resist patterning and etching of the SiN layer. This is followed by depositing the top SiO2 layer and then the conductor patterning. In etching the conductor pattern in the top SiO2 layer, the etching process will be stopped by the SiN layer except where the via holes are already opened in the SiN layer thereby completing the via holes etching in the first SiO2 layer simultaneously.
The creation of a dual damascene structure is highlighted by an example as shown in FIGS. 2a and 2b. 
FIG. 2a gives and overview of the sequence of steps required of forming a Prior Art dual damascene structure. The numbers referred to in the following description of the formation of the dual damascene structure relate to the cross section of the completed dual damascene structure that is shown in FIG. 2b. 
FIG. 2a gives an overview of the sequence of steps required for forming a Prior Art dual damascene structure. The numbers referred to in the following description of the formation of the dual damascene structure relate to the cross section of the completed dual damascene structure that is shown in FIG. 2b. 
FIG. 2a, 52 shows the deposition within plane 29 (FIG. 2b) of a layer of non-metallic material such as poly-silicon on top of the first dielectric 30 and across the via 32, filling the via opening 32.
FIG. 2a, 53 shows the formation of the top section 41 of the dual Damascene structure by forming a pattern 41 within the plane of the non-metallic layer in plane 29. This pattern 41 mates with the pattern of the previously formed via 32 (FIG. 2a, 51) but it will be noted that the cross section of the pattern opening 41 in plane 29 of the non-metallic layer is considerably larger than the cross section of the via opening 32 (FIG. 2a, 51). After pattern 41 has been created and as part of this pattern creation step, the remainder of the non-metallic layer 29 is removed, the pattern 41 remains in place at this time.
FIG. 2a, 54 shows the deposition and planarization (down to the surface of pattern 41) of an inter level dielectric (ILD) 50, a poly-silicon can be used for this dielectric.
FIG. 2a, 55 shows the creation of an opening by removing the poly-silicon from the pattern 41 and the via 32. It is apparent that this opening now has the shape of a T and that the sidewalls of the opening are not straight but show a top section that is larger than the bottom section.
FIG. 2a, 56 shows the deposition of a layer of metal over the surface of the layer 50 of ILD and filling the opening 32/41. FIG. 2b shows the cross section of the dual Damascene structure where a barrier 70 has been formed on the sides of the created opening. The opening 32/41 has previously been created by removing the poly-silicon from the pattern 41 and the vias 32. Metal such as tungsten or copper can be used for the processing step of metal deposition.
Copper is a material that has recently gained much attention as a replacement for conventional interconnect metal. Copper as an interconnect material offers low cost and low resistance, copper however has low adhesive strength to various insulating layers and shows an inherent difficulty in masking and etching a blanket copper layer to form intricate circuit structures. Copper further suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. This corrosion may result in loss of adhesion, delamination, voids and ultimately a catastrophic failure of the component. Copper interconnects should therefore be encapsulated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. Silicon nitride is a diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and the substrate. A typical barrier layer is deposited using rf. sputtering of titanium nitride, tantalum, tungsten, niobium, molybdenum, Ti/TiN or Ti/W and is more preferably formed from TiN. The barrier layer can also be used to improve the adhesion of a subsequent overlying tungsten layer. A barrier layer is preferably about 100 and 500 angstrom thick and more preferably about 300 angstrom thick.
To further enhance the adhesion of a copper interconnect line to the surrounding layer of dielectric or insulation, a seed layer is deposited over the barrier layer. A seed layer can be deposited using a sputter chamber or an Ion Metal Plasma (IMP) chamber at a temperature of between about 0 and 300 degrees C. and a pressure of between about 1 and 100 mTorr, using copper or a copper alloy as the source at a flow rate of between about 10 and 400 sccm and using argon as an ambient gas. The minimum thickness of a seed layer is about 50 Angstrom, this thickness is required to achieve a reliable gap fill.
Semiconductor device performance improvements are largely achieved by reducing device dimensions while increasing device-packaging densities. With the continuing shrinkage of integrated circuit device dimensions, one of the major challenges in creating damascene interconnects is the via resistance of these interconnects. The invention addresses this aspect of the damascene process and provides a method that considerably reduces the via resistance of damascene interconnects.
U.S. Pat. No. 6,015,749 (Liu et al.) shows an ECD Cu and an anneal in a vacuum, see col. 4, line 40.
U.S. Pat. No. 6,043,153 (Nogami et al.) teaches an ECD Cu and vacuum anneal, see col. 4, line 12.
U.S. Pat. No. 6,037,257 (Chiang et al.) shows a Cu sputter deposition and anneal.
U.S. Pat. No. 5,814,557 (Venkatraman et al.) shows another ECD and anneal process.
A principle objective of the invention is to reduce via resistance of damascene interconnects.
Another objective of the invention is to reduce the semiconductor device failure rate that is caused by high damascene via resistance failures.
Yet another objective of the invention is to replace the conventional Electro Chemical Plating (ECP) copper anneal process with an improved process that results in reducing the via resistance of damascene via interconnects.
In accordance with the objectives of the invention a new anneal procedure is introduced that is applied to copper damascene via interconnects after copper ECP deposition and prior to copper planarization.